Yarui Peng Source Confirmed

Affiliation confirmed via AI analysis of OpenAlex, ORCID, and web sources.

Federal Grant PI

Junior Chair Professor

University of Arkansas at Fayetteville

faculty

yrpeng@seu.edu.cn

14 h-index 65 pubs 752 cited

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Biography and Research Information

OverviewAI-generated summary

Yarui Peng's research focuses on the computer-aided design, analysis, and optimization of very-large-scale integration (VLSI) circuits and emerging technologies. His work investigates areas such as 2.5D and 3D integrated circuits (ICs), high band-gap power electronics, and high-efficiency digital and memory systems. Peng has developed methodologies and algorithms for parasitic extraction, signal integrity analysis and optimization, and mitigating reliability issues related to thermal management and power delivery in advanced IC architectures.

His current research includes improving electro-thermal reliability in power systems, specifically multi-chip power modules (MCPMs). This involves MCPM layout synthesis and simultaneous optimization of heat dissipation and electrical performance. Peng is the Principal Investigator on a National Science Foundation (NSF) CAREER grant, totaling $500,000, for research on chiplet-package co-optimizations for 2.5D heterogeneous systems-on-chips (SoCs) with low-overhead inputs/outputs (IOs).

Peng has published extensively, with 65 total publications and 752 citations, and holds an h-index of 14. He collaborates with researchers at the University of Arkansas at Fayetteville, including Imam Al Razi, Quang Trung Le, Tristan M. Evans, and David Huitink.

Metrics

  • h-index: 14
  • Publications: 65
  • Citations: 752

Selected Publications

  • PowerSynth 2: Automated Power Electronics Physical Design Synthesis With Custom and Heterogeneous Components (2025) DOI
  • Adaptive Redistribution Layer Routing for Chiplet-Package Co-Design in 2.5D System (2025) DOI
  • Automated Layout Optimization Methods of a Bidirectional DC-DC ZVS Converter Using PowerSynth (2023) DOI
  • VLSI-Inspired Design Automation for Scalable Power Electronics Layout Optimization (2023) DOI
  • A Comparative Study on Optimization Algorithms in PowerSynth 2 (2023) DOI
  • Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules (2023) DOI
  • Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules (2023) DOI
  • PowerSynth 2: Physical Design Automation for High-Density 3-D Multichip Power Modules (2022) DOI
  • Electromigration-Aware Reliability Optimization of MCPM Layouts Using PowerSynth (2022) DOI
  • Thermal Runaway Mitigation through Electrothermal Constraints Mapping for MCPM Layout Optimization (2022) DOI
  • Design Challenges of Intrachiplet and Interchiplet Interconnection (2022) DOI
  • Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses (2022) DOI
  • Hierarchical Layout Synthesis and Optimization Framework for High-Density Power Module Design Automation (2021) DOI
  • Fast and Accurate Inductance Extraction for Power Module Layout Optimization Using Loop-Based Method (2021) DOI
  • A Scalable In-Context Design and Extraction Flow for Heterogeneous 2.5D Chiplet-Package Co-Optimization (2021) DOI

Federal Grants 1 $500,000 total

NSF PI

CAREER: SHF: Chiplet-Package Co-Optimizations for 2.5D Heterogeneous SoCs with Low-Overhead IOs

Information Technology Researc, Software & Hardware Foundation $500,000

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