Jeff Dix Source Confirmed

Affiliation confirmed via AI analysis of OpenAlex, ORCID, and web sources.

Assistant Professor

University of Arkansas at Fayetteville

faculty

4 h-index 18 pubs 72 cited

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Biography and Research Information

OverviewAI-generated summary

Jeff Dix's research focuses on the design and implementation of low-power analog and mixed-signal integrated circuits, primarily utilizing advanced semiconductor technologies such as 65 nm and 22 nm FD-SOI CMOS. His work has resulted in publications on architectures for artificial neural networks, including analog multilayer perceptrons and spiking neural networks, emphasizing energy efficiency and suitability for hardware accelerators. Dix has also investigated voltage references with high power supply rejection ratio (PSRR) for applications in low-dropout voltage regulators and explored delay-locked loop-based frequency multipliers. His research extends to radio frequency (RF) energy harvesting, with comparisons of rectifier designs. Recent work includes the development of radiation-hardened analog-to-digital converters (ADCs) with fault-tolerant logic for mitigation of single-event upsets (SEUs) and time-interleaved successive approximation register (SAR) ADCs. Dix collaborates with researchers at the University of Arkansas at Fayetteville, including Naveed and John Venker, and has published 18 papers with 72 citations and an h-index of 4.

Metrics

  • h-index: 4
  • Publications: 18
  • Citations: 72

Selected Publications

  • A Radiation-Hardened 4-Bit Flash ADC with Compact Fault-Tolerant Logic for SEU Mitigation (2025) DOI
  • Time-Interleaved SAR ADC in 22 nm Fully Depleted SOI CMOS (2025) DOI
  • Complementary metal-oxide-semiconductor monolithic germanium tin short-wave infrared focal plane array (2025) DOI
  • An efficient wireless sensor node for autonomous sensing in the ISM band (2025) DOI
  • An Ultra-Low-Power 0.8 V, 60 nW Temperature Sensor for Battery-Less Wireless Sensor Networks (2025) DOI
  • Low-Power, High-Speed Adder Circuit Utilizing Current-Starved Inverters in 22 nm FDSOI (2025) DOI
  • A 0.8 V Bandgap Voltage Reference with High PSRR for Low-Dropout Voltage Regulator in 22nm FD-SOI (2024) DOI
  • Design of a Low-Power Delay-Locked Loop-Based 8× Frequency Multiplier in 22 nm FDSOI (2023) DOI
  • A Low-Power Analog Cell for Implementing Spiking Neural Networks in 65 nm CMOS (2023) DOI
  • Programmable Energy-Efficient Analog Multilayer Perceptron Architecture Suitable for Future Expansion to Hardware Accelerators (2023) DOI
  • Comparison of Two RF Rectifiers Designed in FDSOI 22nm for RF Energy Harvesting (2022) DOI
  • A Resistor-less, Nano-Watt CMOS Voltage Reference with High PSRR (2021) DOI

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